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L6562A
Transition-mode PFC controller
Features

Proprietary multiplier design for minimum THD Very accurate adjustable output overvoltage protection Ultra-low (30A) Start-up current Low (2.5mA) quiescent current Digital leading-edge blanking on current sense Disable function on E/A input 1% (@ TJ = 25 C) internal reference voltage -600/+800mA totem pole gate driver with active pull-down during UVLO and voltage clamp DIP-8/SO-8 packages Block diagram
DIP-8 SO-8
Applications
PFC pre-regulators for:

IEC61000-3-2 compliant SMPS (Flat TV, monitors, desktop PC, games) HI-END AC-DC adapter/charger up to 400W Electronic ballast Entry level server & web server
Figure 1.
Table 1. Device summary
Order codes L6562AN L6562AD L6562ADTR August 2007 Package DIP-8 SO-8 SO-8 Rev 3 Packaging Tube Tube Tape & Reel 1/26
www.st.com 26
Contents
L6562A
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 4 5 6 7
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Typical electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1 7.2 7.3 7.4 7.5 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Operating with no auxiliary winding on the boost inductor . . . . . . . . . . . . 16 Comparison between the L6562A and the L6562 . . . . . . . . . . . . . . . . . . 17
8 9 10
Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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L6562A
Description
1
Description
The L6562A is a current-mode PFC controller operating in Transition Mode (TM). Coming with the same pin-out as its predecessors L6561 and L6562, it offers improved performance. The highly linear multiplier includes a special circuit, able to reduce AC input current distortion, that allows wide-range-mains operation with an extremely low THD, even over a large load range. The output voltage is controlled by means of a voltage-mode error amplifier and an accurate (1% @TJ = 25C) internal voltage reference. The device features extremely low consumption (60A max. before start-up and <5 mA operating) and includes a disable function suitable for IC remote ON/OFF, which makes it easier to comply with energy saving requirements (Blue Angel, EnergyStar, Energy2000, etc.). An effective two-step OVP enables to safely handle overvoltages either occurring at start-up or resulting from load disconnection. The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable to drive high current MOSFETs or IGBTs. This, combined with the other features and the possibility to operate with the proprietary Fixed-Off-Time control, makes the device an excellent low-cost solution for EN61000-3-2 compliant SMPS in excess of 350W.
3/26
Pin settings
L6562A
2
2.1
Pin settings
Pin connection
Figure 2. Pin connection (top view)
INV COMP MULT CS
1 2 3 4
8 7 6 5
Vcc GD GND ZCD
2.2
Pin description
Table 2. Pin description
Pin N 1 Name INV Description Inverting input of the error amplifier. The information on the output voltage of the PFC pre-regulator is fed into this pin through a resistor divider. The pin doubles as an ON/OFF control input. Output of the error amplifier. A compensation network is placed between this pin and INV to achieve stability of the voltage control loop and ensure high power factor and low THD. Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal sinusoidal-shaped reference, generated by the multiplier, to determine MOSFET's turn-off. The pin is equipped with 200 ns leading-edge blanking for improved noise immunity. Boost inductor's demagnetization sensing input for transition-mode operation. A negative-going edge triggers MOSFET's turn-on. Ground. Current return for both the signal part of the IC and the gate driver. Gate driver output. The totem pole output stage is able to drive power MOSFET's and IGBT's with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is clamped at about 12V to avoid excessive gate voltages in case the pin is supplied with a high Vcc. Supply Voltage of both the signal part of the IC and the gate driver. The supply voltage upper limit is extended to 22V min. to provide more headroom for supply voltage changes.
2
COMP
3
MULT
4
CS
5 6
ZCD GND
7
GD
8
Vcc
4/26
L6562A
Maximum ratings
3
Maximum ratings
Table 3. Absolute maximum ratings
Symbol VCC IGD --IZCD Pin 8 7 1 to 4 5 Parameter IC supply voltage (ICC 20mA) Output totem pole peak current Analog inputs & outputs Zero current detector max. current Value Self-limited Self-limited -0.3 to 8 10 Unit V A V mA
4
Thermal data
Table 4. Thermal data
Value Symbol RthJA PTOT TJ TSTG Parameter SO8 Max. Thermal Resistance, Junction-toambient Power Dissipation @TA = 50C Junction Temperature Operating range Storage Temperature 150 0.65 -40 to 150 -55 to 150 DIP8 100 1 C/W W C C Unit
5/26
Electrical characteristics
L6562A
5
Electrical characteristics
Table 5. Electrical characteristics ( -25C < TJ < +125C, VCC = 12V, Co = 1nF; unless otherwise specified)
Symbol Supply voltage VCC VccOn VccOff Hys VZ Operating range Turn-on threshold Turn-off threshold Hysteresis Zener Voltage ICC = 20mA After turn-on
(1) (1)
Parameter
Test condition
Min
Typ
Max
Unit
10.5 11.7 9.5 2.2 22.5 25 12.5 10
22.5 13.3 10.5 2.8 28
V V V V V
Supply current Istart-up Iq ICC Iq Start-up current Quiescent current Before turn-on, VCC = 11V After turn-on 30 2.5 3.5 1.7 60 3.75 5 2.2 A mA mA mA
Operating supply current @ 70kHz Quiescent current During OVP (either static or dynamic) or VINV 150mV
Multiplier input IMULT VMULT V cs -------------------V MULT K Input bias current Linear operation range Output max. slope Gain (2) VMULT = 0 to 1V, VCOMP = Upper clamp VMULT = 1V, VCOMP= 4V, VMULT = 0 to 4V 0 to 3 1 0.32 1.1 0.38 0.44 -1 A V V/V V
Error amplifier VINV Voltage feedback input threshold Line regulation IINV Gv GB ICOMP Input bias current Voltage gain Gain-bandwidth product Source current Sink current VCOMP = 4V, VINV = 2.4V VCOMP = 4V, VINV = 2.6V -2 2.5 TJ = 25 C 10.5V < VCC < 22.5V (1) VCC = 10.5V to 22.5V VINV = 0 to 3V Open loop 60 80 1 -3.5 4.5 -5 2.475 2.455 2 2.5 2.525 V 2.545 5 -1 mV A dB MHz mA mA
6/26
L6562A Table 5. Electrical characteristics (continued) ( -25C < TJ < +125C, VCC = 12V, Co = 1nF; unless otherwise specified)
Symbol VCOMP VINVdis VINVen Parameter Upper clamp voltage Lower clamp voltage Disable threshold Restart threshold Test condition ISOURCE = 0.5mA ISINK = 0.5mA (1)
Electrical characteristics
Min 5.3 2.1 150 380
Typ 5.7 2.25 200 450
Max 6 2.4 250 520
Unit V V mV mV
Output overvoltage IOVP Hys Dynamic OVP triggering current Hysteresis Static OVP threshold Current sense comparator ICS tLEB td(H-L) VCS Vcsoffset Input bias current Leading edge blanking Delay to output Current sense clamp Current sense offset VCOMP = Upper clamp, Vmult = 1.5V VMULT = 0 VMULT = 2.5V 1.0 VCS = 0 100 200 175 1.08 25 mV 5 1.16 -1 300 A ns ns V
(3) (1)
23.5
27 20
30.5
A A
2.1
2.25
2.4
V
Zero current detector VZCDH VZCDL VZCDA VZCDT IZCDb IZCDsrc IZCDsnk Starter tSTART Start timer period 75 190 300 s Upper clamp voltage Lower clamp voltage Arming voltage (positive-going edge) Triggering voltage (negative-going edge) Input bias current Source current capability Sink current capability IZCD = 2.5mA IZCD = - 2.5mA
(3)
5.0 -0.3
5.7 0 1.4 0.7 2
6.5 0.3
V V V V A mA mA
(3)
VZCD = 1 to 4.5V -2.5 2.5
7/26
Electrical characteristics Table 5. Electrical characteristics (continued) ( -25C < TJ < +125C, VCC = 12V, Co = 1nF; unless otherwise specified)
Symbol Gate driver VOL VOH Isrcpk Isnkpk tf tr VOclamp Output low voltage Output high voltage Peak source current Peak sink current Voltage fall time Voltage rise time Output clamp voltage UVLO saturation
1. All the parameters are in tracking 2. The multiplier output is given by:
L6562A
Parameter
Test condition
Min
Typ
Max
Unit
Isink = 100mA Isource = 5mA 9.8 -0.6 0.8
0.6 10.3
1.2
V V A A
30 60 Isource = 5mA; Vcc = 20 V Vcc = 0 to VCCon, Isink = 2 mA 10 12
70 110 15 1.1
ns ns V V
Vcs = K VMULT (VCOMP - 2.5 )
3. Parameters guaranteed by design, functionality tested in production.
8/26
L6562A
Typical electrical characteristic
6
Typical electrical characteristic
Figure 3.
10.00
Supply current vs supply voltage
Figure 4.
13
Start-up & UVLO vs TJ
p j
Vcc-ON
1.00
12
Icc (mA)
(V)
0.10
11
0.01 Co = 1 nF f = 70 kHz Tj = 25C 0.00 0.00
10 Vcc-OFF
9
5.00
10.00 Vcc (V)
15.00
20.00
25.00
-50
0
50 Tj (C)
100
150
Figure 5.
10
IC consumption vs TJ
p j
Figure 6.
28
Vcc Zener voltage vs TJ
Operating Quiescent Disabled or during OVP
27
1 Icc (mA)
VccZ (V)
26
25
0.1
Vcc = 12 V Co= 1 nF f = 70 kHz
24
23
Before start-up
22 -50 0 50 Tj (C) 100 150
0.01 -50 0 50 Tj (C) 100 150
9/26
Typical electrical characteristic
L6562A
Figure 7.
2.6
Feedback reference vs TJ
Figure 8.
35 34 33
OVP current vs TJ
j Vcc = 12V
Vcc = 12V
2.55
32 31
VREF (V)
Iovp (uA)
30 29 28 27
2.5
2.45
26 25 24
2.4 -50 0 50 Tj (C) 100 150
23 -50 0 50 Tj (C) 100 150
Figure 9.
6
E/A output clamp levels vs TJ Figure 10. Delay-to-output vsTJ
300
Upper clamp 5
200
V COMP pin2 (V)
4 Vcc = 12V 3 Lower clamp 2
tD (H-L) (ns)
Vcc = 12V
100
0
1 -50 0 50
Tj (C)
-50
0
100
150
50 Tj (C)
100
150
10/26
L6562A
Typical electrical characteristic
Figure 11. Multiplier characteristic
p 1.2 1.1 1.0 0.9 0.8 Vcs (pin4) (V) Upper Volt. Clamp 5.75 V 4V 5V 4.5V 3.5V V COMP (pin2) (V)
Figure 12. Vcs clamp vs TJ
1.3 Vcc = 12V VCOMP = Upper clamp
1.2 Vcsx (V)
3V
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 0 0.2 0.4 0.6 0.8
1.1
2.5 V
1
1 1.2 1.4 1.6 1.8 2 VMULT (pin3) (V) 2.2 2.4 2.6 2.8 3
-50
0
50 Tj (C)
100
150
Figure 13. ZCD clamp levels vs TJ
p j 7 6 5 4 Vzcd (V) 3 2 1 0 -1 -50 0 50 Tj (C) 100 150 Lower clamp Vcc = 12V IZCD = 2.5 mA Upper clamp
Figure 14. Start-up timer vs TJ
p j 200
190
Tstart (us)
180
170
Vcc = 12V
160
150 -50 0 50 Tj (C) 100 150
11/26
Typical electrical characteristic
L6562A
Figure 15. Gate-driver output low saturation
5.00
Figure 16. Gate-drive output high saturation
12.00 Tj = 25 C
4.00
11.00
Vcc = 12V SOURCE
10.00
3.00
Vpin7 (V)
Vpin7 (V)
9.00
2.00
8.00
Tj = 25 C 1.00 Vcc = 12V SINK 0.00 0 200 400
I GD (m A)
7.00
6.00
600
800
1000
0
200 I GD (mA)
400
600
Figure 17. Gate-drive clamp vs TJ
13.5 Vcc = 20V
Figure 18. Output gate drive low saturation vs TJ during UVLO
1.1 Isink = 2 mA Vcc = 11V 0.9 Vpin7 (V) Vcc = 0V 0.8
1
13.25
Vpin7 clamp (V)
13
0.7
12.75
0.6
12.5 -50 0 50 Tj (C) 100 150
0.5 -50 0 50 Tj (C) 100 150
12/26
L6562A
Application information
7
7.1
Application information
Overvoltage protection
Under steady-state conditions, the voltage control loop keeps the output voltage Vo of a PFC pre-regulator close to its nominal value, set by the resistors R1 and R2 of the output divider. Neglecting ripple components, the current through R1, IR1, equals that through R2, IR2. Considering that the non-inverting input of the error amplifier is internally referenced at 2.5V, also the voltage at pin INV will be 2.5V, then:
Equation 1
V O - 2.5 I R2 = I R1 = 2.5 = --------------------------R1 R2
If the output voltage experiences an abrupt change Vo > 0 due to a load drop, the voltage at pin INV will be kept at 2.5V by the local feedback of the error amplifier, a network connected between pins INV and COMP that introduces a long time constant to achieve high PF (this is why Vo can be large). As a result, the current through R2 will remain equal to 2.5/R2 but that through R1 will become:
Equation 2
V O - 2.5 + V O I' R1 = --------------------------------------R1
The difference current IR1=I'R1-IR2=I'R1-IR1= Vo/R1 will flow through the compensation network and enter the error amplifier output (pin COMP). This current is monitored inside the device and if it reaches about 24A the output voltage of the multiplier is forced to decrease, thus smoothly reducing the energy delivered to the output. As the current exceeds 27A, the OVP is triggered (Dynamic OVP): the gate-drive is forced low to switch off the external power transistor and the IC put in an idle state. This condition is maintained until the current falls below approximately 7A, which re-enables the internal starter and allows switching to restart. The output Vo that is able to trigger the Dynamic OVP function is then:
Equation 3
VO = R1 * 20 * 10 - 6
An important advantage of this technique is that the OV level can be set independently of the regulated output voltage: the latter depends on the ratio of R1 to R2, the former on the individual value of R1. Another advantage is the precision: the tolerance of the detection current is 13%, i.e. 13% tolerance on Vo. Since Vo << Vo, the tolerance on the absolute value will be proportionally reduced. Example: Vo = 400V, Vo = 40V. Then: R1 = 40V/27A 1.5M ; R2 = 1.5 M *2.5/(400-2.5) = 9.43k. The tolerance on the OVP level due to the L6562A will be 40*0.13 = 5.3V, that is 1.2%.
13/26
Application information
L6562A
When the load of a PFC pre-regulator is very low, the output voltage tends to stay steadily above the nominal value, which cannot be handled by the Dynamic OVP. If this occurs, however, the error amplifier output will saturate low; hence, when this is detected the external power transistor is switched off and the IC put in an idle state (Static OVP). Normal operation is resumed as the error amplifier goes back into its linear region. As a result, the device will work in burst-mode, with a repetition rate that can be very low. When either OVP is activated the quiescent consumption of the IC is reduced to minimize the discharge of the Vcc capacitor and increase the hold-up capability of the IC supply system.
7.2
Disable function
The INV pin doubles its function as a not-latched IC disable: a voltage below 0.2V shuts down the IC and reduces its consumption at a lower value. To restart the IC, the voltage on the pin must exceed 0.45 V. The main usage of this function is a remote ON/OFF control input that can be driven by a PWM controller for power management purposes. However it also offers a certain degree of additional safety since it will cause the IC to shutdown in case the lower resistor of the output divider is shorted to ground or if the upper resistor is missing or fails open.
7.3
THD optimizer circuit
The device is equipped with a special circuit that reduces the conduction dead-angle occurring to the AC input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (Total Harmonic Distortion) of the current is considerably reduced. A major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very low. This effect is magnified by the highfrequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop.
14/26
L6562A
Application information Figure 19. THD optimization: standard TM PFC controller (left side) and L6562A (right side)
Input current
Input current
Rectified mains voltage
Rectified mains voltage
Imains Input current
MOSFET's drainVdrain voltage
Input current MOSFET's drainVdrain voltage
Imains
To overcome this issue the circuit embedded in the device forces the PFC pre-regulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. This will result in both minimizing the time interval where energy transfer is lacking and fully discharging the high-frequency filter capacitor after the bridge. The effect of the circuit is shown in figure 2, where the key waveforms of a standard TM PFC controller are compared to those of the L6562A. Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. To maximally benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself even with an ideal energy transfer by the PFC pre-regulator - thus making the action of the optimizer circuit little effective.
15/26
Application information
L6562A
7.4
Operating with no auxiliary winding on the boost inductor
To generate the synchronization signal on the ZCD pin, the typical approach requires the connection between the pin and an auxiliary winding of the boost inductor through a limiting resistor. When the device is supplied by the cascaded DC-DC converter, it is necessary to introduce a supplementary winding to the PFC choke just to operate the ZCD pin. Another solution could be implemented by simply connecting the ZCD pin to the drain of the power MOSFET through an R-C network as shown in figure 3: in this way the highfrequency edges experienced by the drain will be transferred to the ZCD pin, hence arming and triggering the ZCD comparator. Also in this case the resistance value must be properly chosen to limit the current sourced/sunk by the ZCD pin. In typical applications with output voltages around 400V, recommended values for these components are 22pF (or 33pF) for CZCD and 330k for RZCD. With these values proper operation is guaranteed even with few volts difference between the regulated output voltage and the peak input voltage
Figure 20. ZCD pin synchronization without auxiliary winding
RZCD ZCD 5
CZCD
L6562A
16/26
L6562A
Application information
7.5
Comparison between the L6562A and the L6562
The L6562A is not a direct drop-in replacement of the L6562, even if both have the same pin-out. One function (Disable) has been relocated. Table 2 compares the two devices, i.e. those parameters that may result in different values of the external components. The parameters that have the most significant impact on the design, i.e. that definitely require external component changes when converting an L6562based design to the L6562A, are highlighted in bold.
Table 6. L6562A vs. L6562
Parameter IC turn-on & turn-off thresholds (typ.) Turn-off threshold spread (max.) IC consumption before start-up (max.) Multiplier gain (typ.) Current sense reference clamp (typ.) Current sense propagation delay (delay-to-output) (typ.) Dynamic OVP triggering current (typ.) ZCD arm/trigger/clamp thresholds (typ.) Enable threshold (typ.) Gate-driver internal drop (max.) Leading-edge blanking on current sense Reference voltage accuracy ( overall)
1. Function located on pin 5 (ZCD) 2. Function located on pin 1 (INV)
L6562 12/9.5 V 0.8 V 70 uA 0.6 1.7 V 200 ns 40 uA 2.1/1.4/0.7 V 0.3 V (1) 2.6 V No 2.4%
L6562A 12.5/10 V 0.5 V 60 uA 0.38 1.08 V 175 ns 27 uA 1.4/0.7/0 V 0.45 V (2) 2.2 V Yes 1.8%
The lower value (-36%) for the clamp level of the current sense reference voltage allows the use of a lower sense resistor for the same peak current, with a proportional reduction of the associated power dissipation. Essentially, the advantage is the reduction of the power dissipated in a single point (hotspot), which is a considerable benefit in applications where heat removal is critical, e.g. in adapters enclosed in a sealed plastic case. The lower value for the Dynamic OVP triggering current allows the use of a higher resistance value (+48%) for the upper resistor of the divider sensing the output voltage of the PFC stage (keeping the same overvoltage level) with no significant increase of noise sensitivity. This reduction goes in favor of standby consumption in applications required to comply with energy saving regulations.
17/26
Application examples and ideas
L6562A
8
Application examples and ideas
Figure 21. Demo board EVL6562A-TM-80W, wide-range mains : electrical schematic
D1 NTC STTH1L06 2.5 R4 R5 270 k 270 k D8 1N4148 D2 1N5248B C5 10 nF R14 100 T1 R11 1M R50 - 22 k R6 47 k ZCD R2 1 M VCC MULT 8 3 5 COMP 2 C3 - 2200 nF C23 150 nF 1 7 4 CS GD R12 1M Vo=400V Po=80W
R1 1 M
F1 4A/250V Vac 88V to 264V
+
P1 W08
C1 0.22 F 630V
INV R7 33
-
L6562A
6 GND
Q1 STP8NM50FP
C6 47 F 450V
R3 15 k
C2 10nF
R8 47k R15 R9 0.68 0.25W R10 0.68 0.25W R13 15 k R13B 82 k
C29 22 F 25V
C4 100 nF
SHORTED
Boost Inductor Spec (ITACOIL E2543/E) E25x13x7 core, N67 ferrite 1.5 mm gap for 0.7 mH primary inductance Primary: 102 turns 20x0.1 mm Secondary: 10 turns 0.1 mm
18/26
L6562A
Application examples and ideas
Figure 22. L6562A 80W TM PFC evaluation Figure 23. L6562A 80W TM PFC evaluation board: compliance to EN61000-3-2 board: compliance to JEIDA-MITI standard standard
Measurements @ 230Vac Full load 1 Harmonic current (A) EN61000-3-2 class D limits
Measurements @ 100Vac Full load 1 Harmonic current (A)
JEIDA-MITI class D limits
0.1
0.1
0.01
0.01
0.001
0.001
0.0001 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Harmonic Order (n)
0.0001 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Harmonic Order (n)
Vin = 230 Vac - 50 Hz, Pout = 80 W THD = 10.48 %, PF = 0.973
Vin = 100 Vac - 50 Hz, Pout = 80 W THD = 3.18 %, PF = 0.997
Figure 24. Figure 3 - L6562A 80W TM PFC Evaluation board: Input Current waveform @230V-50Hz - 80W load
Figure 25. Figure 4- L6562A 80W TM PFC Evaluation board: Input Current waveform @100V-50Hz - 80W load
19/26
Application examples and ideas
L6562A
Figure 26. L6562A 80W TM PFC evaluation board: Power Factor vs Vin
1.00
Figure 27. L6562A 80W TM PFC evaluation board: THD vs Vin
12
10
0.95
8 THD (%)
PF
0.90
Pout = 80W
6
4
0.85
2
Pout = 80W
0.80 80 100 120 140 160 180 Vin (Va c) 200 220 240 260
0 80 100 120 140 160 180 Vin (Vac) 200 220 240 260
Figure 28. L6562A 80W TM PFC evaluation board: efficiency vs Vin
Figure 29. L6562A 80W TM PFC Evaluation board: Static Vout regulation vs Vin
404
100
403.5
95
403
EFFICIENCY (%)
Pout = 80W
90
Vout (Vdc) 402.5
85
Pout = 80W
402
401.5
80
401
400.5
75 80 100 120 140 160 180 200 220 240 260
400 80 100 120 140 160 180 Vin (Vac) 200 220 240 260
Vin (Vac)
20/26
L6562A
JP1 01 JUMPER D1 2 D2 D1 5XB6 0 5-6 D3 STTH8R06 C6 470nF-630V R2 NTC 2R5-S237 C7 330uF-450V + C4 470nF-630V ~ 1 JP1 02 JUMPER 2 470nF-630V C5 8 11 ~ C3 680nF-X2 1N5406 L3 DM-51uH-6A L4 PQ40-500u H 1-2 +40 0Vdc 1 CM-1.5mH-5A L1 C1 470nF-X2 470nF-X2 C2 L2 RES
F1
J1
90 - 265Vac
1
8A/250V
R1
2
1M5
1 2 3 4 5
+
R3 180K R5 47R
+40 0Vdc R1 0 D4 LL4148 750k R1 1 680k C1 1 470nF/5 0V C1 3 220nF 9.1k R3 6 3R9 1 R14 39k R1 2 47uF/50 V C1 2 D5 BZX8 5-C15
R4 180K
C1 0 33N
C1 4 3.3uF
D7 LL4148
INV COMP MULT CS L6562A
R1 5 820 R3 1 1K5 C1 6 220pF R1 6 15K
VCC GD GND ZCD
5 C1 5 100pF 6 LL4148 D6 7
8 R1 7 6R8 Q1 STP12NM5 0FP
2 3 4
R3 5 3R9
D8 LL4148 Q2 STP12NM5 0FP R1 8 6R8
R1 9 1K0 C2 0 Q3 BC85 7C 330pF R2 0 0R39-1W R2 1 0R39-1W R2 2 0R39-1W R2 3 0R68W
R3 2
R3 3
620k R3 4 10k 10nF C2 1
620k
Application examples and ideas
Figure 30. Demo board EVL6562A-400W, wide-range mains, FOT: electrical schematic
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Package mechanical data
L6562A
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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L6562A Table 7. DIP-8 mechanical data
mm Dim. Min A Typ 3.32 Max Min
Package mechanical data
Inch Typ 0.131 Max
a1 B b b1 D E e e3 e4 F I L Z
0.51 1.15 0.356 0.204 1.65 0.55 0.304 10.92 7.95 2.54 7.62 7.62 6.6 5.08 3.18 3.81 1.52 9.75
0.020 0.045 0.014 0.008 0.065 0.022 0.012 0.430 0.313 0.100 0.300 0.300 0.260 0.200 0.125 0.150 0.060 0.384
Figure 31. Package dimensions
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Package mechanical data
L6562A
Table 8. SO-8 mechanical data
mm. Dim. Min A 1.35 Typ Max 1.75 Min 0.053 Typ Max 0.069 inch
A1 A2 B C
D
0.10 1.10 0.33 0.19 4.80 3.80 1.27 5.80 0.25 0.40
0.25 1.65 0.51 0.25 5.00 4.00
0.004 0.043 0.013 0.007 0.189 0.15 0.050
0.010 0.065 0.020 0.010 0.197 0.157
(1)
E e H h L k ddd
6.20 0.50 1.27
0.228 0.010 0.016
0.244 0.020 0.050
0 (min.), 8 (max.) 0.10 0.004
1. Dimensions D does not include mold flash, protru-sions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm (.006inch) in total (both side).
Figure 32. Package dimensions
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L6562A
Revision history
10
Revision history
Table 9. Revision history
Date 03-Mar-2007 28-Jun-2007 07-Aug-2007 Revision 1 2 3 First release Updated electrical characteristics Added Chapter 6: Typical electrical characteristic on page 9 Changes
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L6562A
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